1. Field of the Invention
The present invention relates to a lead frame for a semiconductor package, and more particularly, to a lead frame for a semiconductor package which can maintain a high quality of the package under a high-temperature environment even if a plating layer is thin, can prevent migration of silver (Ag) due to a reduction in the thickness of an Ag-plated layer, and can reduce the manufacturing cost.
2. Description of the Related Art
A semiconductor lead frame basically includes a die pad unit for mounting a semiconductor memory chip and fixing the same at a static state, an inner lead connected to the chip by wire bonding, and an outer lead for connection with an external circuit. The wire-bonded chip and the wire-bonded inner lead are hermetically sealed by a molding compound to form a semiconductor package. The semiconductor lead frame having the aforementioned configuration is generally manufactured by a stamping process or an etching process.
In such a lead frame for a semiconductor package, in order to maintain good wire bondability in an inner lead and good adhesion between a pad and a chip, a metal material such as silver (Ag) is plated on the pad and the tip of the inner lead of the lead frame. Also, after resin passivation film molding, in order to improve solderability during mounting an outer lead connected to an external circuit board, solder plating, that is, tin-lead (Sn-Pb) plating, is performed on a predetermined region of the outer lead. However, since the plating is generally performed in a wet process after resin passivation film molding, a Snxe2x80x94Pb plating solution soaks through a gap between epoxy and lead, which degrades the reliability of completed products. In order to solve this problem, a pre plating method (pre plated frame) has been proposed. In the pre plated frames, prior to semiconductor packaging, a metal having excellent wire bondability, chip adhesion and solder wettability is pre plated on a metal material, thereby omitting a lead plating step during a semiconductor post packaging process. Thus, since use of the pre plated lead frames simplifies the semiconductor post packaging process and environmental contamination due to lead plating can be reduced, much attention has recently been paid to the pre plated frames.
Considering that a semiconductor assembling process including semiconductor chip adhesion, wire bonding, epoxy molding, soldering and the like, is generally performed at a high temperature of 200xc2x0 C. or higher, the kind of an outer plating layer is quite an important factor in manufacturing a lead frame by a preplating method. Requirements for an outer plating layer of a lead frame manufactured by a pre plating method include oxidation resistance at a higher temperature, good bondability with a bonded wire used in wire bonding, good adhesion with a chip, generally made of silicon, good moldability with an epoxy resin which is a molding material, good fusibility with lead during soldering. In addition, in order to prevent abrasion of a bonding capillary during wire bonding, the outer plating layer should be made of metal having adequate ductility. The long-term reliability of a semiconductor device must be ensured, without short-circuiting due to diffusion of plated metal in the outer layer into a medium in contact therewith under hot and humid conditions for a long period of time, which is so-called xe2x80x9cmigration.xe2x80x9d The outer plating layer material satisfying the requirements is a noble metal such as palladium (Pd), gold (Au) or silver (Ag). Specifically, Au and Ag have been conventionally preferred due to their excellent conductivity and ductility. In the case of using Au, 0.5 to 2 xcexcm thick Au is preferably plated. In the case of using Ag, 1 to 5 xcexcm thick Ag is preferably plated. However, as a semiconductor package has recently been miniaturized and highly integrated, Pd, which has a denser structure and which does not cause migration, has gained more attention as an outer plating layer material than Au or Ag causing migration.
However, in the case of plating the noble metal, in order to maintain flatness of a plating layer and to reduce the amount of a noble metal used, an underlying plating layer made of a metal having a good plating adhesion strength to the material to be plated thereon, is first formed and noble metal plating is then performed on the underlying plating layer. Here, nickel (Ni) is widely used as a material of the underlaying plating layer.
FIGS. 1 through 4 show the structure of a plating layer of a conventional semiconductor lead frame based on a pre plated method.
First, FIG. 1 shows a cross-section of a conventional semiconductor lead frame disclosed in Japanese Patent No. 1,501,723, directed to a lead frame for a plastic package in which a Ni underlying plating layer 12 is formed on a chip mount section and a lead frame surface 11 of a wire bonding section, and a plating layer 13 made of a Pd or Pd alloy is formed as an outer layer. In one embodiment of this patent, 0.1 to 1 xcexcm thick Pd plated layer is formed on Ni plated layer, 0.1 to 1 xcexcm thick. According to this patent, in the case of thickly plating Au or Ag as the outer layer (Au: 0.5 to 2 xcexcm; Ag: 1 to 5 xcexcm), the migration problem can be prevented.
Pd has a very dense structure and is a very hard metal. Further, when the outer layer is made of Pd, it is likely to be oxidized in the course of a high temperature semiconductor packaging process. Thus, the plating layer gets harder and the melting point thereof gets higher, thereby lowering solderability and causing wearing or damage of a wire bonding capillary. Also, since Pd is a metal having a hydrogen embrittlement, it is combined with hydrogen when exposed to the atmosphere, resulting in brittleness of the plating layer.
FIG. 2 shows a cross section of a conventional semiconductor lead frame disclosed in Japanese Patent No. 2,543,619, which is proposed for overcoming the problems with the structure disclosed in Japanese Patent No. 1,501,723, and in which there is provided a lead frame for a semiconductor device having a plurality of metal coated layers on a copper (Cu) or Cu alloy layer, wherein a Ni underlying plating layer 22 is disposed on the Cu or Cu alloy layer 21, a 0.3 xcexcm or less thick Pd or Pd alloy layer is 23 is entirely formed thereon and 0.001 to 0.1 xcexcm thick Au plated layer 24 is formed on the Pd or Pd alloy layer on an outer lead of the lead frame.
However, in the case where the semiconductor lead frame having the stacked structure shown in FIG. 2 is applied to a semiconductor package requiring high reliability, the following problems may occur. First, a lead frame having an Au plated layer as the outer plating layer is comparatively weaker than the lead frame having an Ag outer plating layer in view of adhesion of a wire bonding portion, so that cracks are generated at the wire bonding portion after packaging the semiconductor device, causing product defects such as short-circuiting. This is due to repeated thermal shock applied to a lead frame having relatively weaker molding adhesion, causing repetition of feeble fluctuation between the mold portion and a lead frame bonding surface and generating fatigue therefrom. Further, the cracks generated due to fatigue may result in short-circuiting. As described above, repetition of contraction and expansion, due to repeated thermal stress, generates cracks at the interface between a mold and a lead frame or cutting of a wire bonding portion, which is called a xe2x80x9cheel crack.xe2x80x9d Crack resistance tests were carried out for the lead frame having the above-described structure, and the results thereof showed that cracks were generated at 600 TC. cycles or below, as will be described in Comparative Example 1, which is very poor compared to the crack resistance in the case of using Ag as the outer plating layer, in which cracks were generated at over 1000 TC. cycles. Thus, the semiconductor product having the aforementioned structure has a problem in attaining long-term reliability.
Another example of a conventional pre plated lead frame is disclosed in U.S. Pat. No. 4,529,667, shown in FIG. 3.
Referring to FIG. 3, an underlying plating layer 32 made of Ni is stacked on a metal substrate 31 made of Cu or Cu alloy to a thickness of 0.1 to 5 gm. A 0.01 to 2 xcexcm thick intermediate plating layer 33 made of Sn, Pd, Ru, Cd or alloys thereof is formed on the underlying plating layer 32. A 1 to 3 xcexcm outer plating layer 34 made of Ag or Ag alloy is then formed on the intermediate plating layer 33.
However, since the lead frame having the above-described stacked structure has an overly thick intermediate plating layer made of Pd or Pd alloy, cracks may generate at a lead bent portion. Also, the overall thickness of the plating layers formed on the metal substrate totals 1.11 to 10 xcexcm. In consideration of the current trend for multi pin, light-weight lead frames, the thickness of each plating layer and the overall thickness of various plating layers become excessive. Thus, when the aforementioned lead frame is applied to a multi pin device having more than 100 pins, the following problem may be generated.
In other words, in the case where the Ag plated layer is thick, the chip reliability is lowered due to migration of Ag plated under hot and humid conditions after semiconductor packaging. Also, excessive use of expensive noble metal, Pd or Ag, increases the manufacturing cost of the lead frame.
In the lead frames having the structures shown in FIGS. 1 through 3, plating layers such as a Ni plated layer, a Pd plated layer, an Ag plated layer or an Au plated layer are generally plated using a direct-current (DC) current method. However, if the Pd, Ag or Au plated layer is formed by the DC current method, the ductility of the plating layer may deteriorate, so that it is highly probable to generate cracks during formation. Also, a thickness deviation may be generated due to nonuniform plating speeds. Thus, if the thickness of a plating layer is reduced to 1 xcexcm (4 microinches) or less, the interface inhomogeneity becomes severe so that the plating layer cannot function as an oxidation stopping layer. Thus, the intermediate plating layer or metal substrate may be oxidized during high-temperature semiconductor packaging, or metallic elements may diffuse into the surface to then be oxidized in the air, thereby generating bending cracks or lowering the solderability of the lead frame. To prevent these problems, the plating layer may be formed thickly or post treatment such as annealing may be performed, which increases, however, the manufacturing cost of the lead frame.
FIG. 4 shows the stacked structure of another conventional lead frame, disclosed in U.S. Pat. No. 6,150,713 by the applicant of the present invention. Referring to FIG. 4, a Ni plated layer 42 made of Ni or Ni alloy is formed on a metal substrate 41, a protection layer 43 plated with at least one metal among Pd, Au, Ag and alloys thereof is formed on the Ni plated layer 42 to a thickness of 0.025-0.05 xcexcm (0.01 to 1.5 microinches). The protection layer 43 is formed by submerging the metal substrate having the Ni plated layer formed thereon, into a plating bath having a plating solution containing at least one among Pd, Au, Ag and alloys thereof and then applying a modulated current to the plating bath.
If the lead frame having the above-described stacked structure, that is, the lead frame having the protection layer having the aforementioned thickness and component, is applied to a semiconductor packaging process performed at 150 to 300xc2x0 C., the following problems are involved. First, in the case of a Pd protection layer, wire bondability and solderability are lowered due to thermal oxidation of the surface layer at a high temperature condition. In the case of an Au protection layer having relatively weak molding adhesion, when it is applied to a packaging process requiring high-level reliability to be subjected to repeated thermal loads, feeble fluctuation occurs between mold-bonding portions. Thus, there is a high probability of generating heel crack at a wire bonding portion. Also, in the case of an Ag protection layer, it is difficult to directly plate Ag on a Ni underlying plating layer. Even if Ag is directly plated, adhesion between the Ag protection layer and the Ni plated layer is poor, thereby unavoidably lowering the wire bondability.
To solve the above problems, it is an object of the present invention to provide a lead frame for a semiconductor package, which can improve the characteristics of various plating layers in such a manner that an underlying plating layer made of a Ni or Ni alloy is formed on the lead frame, an outer plating layer made of Ag or Ag alloy having excellent physical property as a pre plated lead frame material is then formed, an intermediate plating layer made of Pd or Pd alloy is formed between the underlying plating layer and the outer plating layer, which can improve the solderability, wire bondability and epoxy adhesion of the pre plated lead frame by reducing the thicknesses of the plating layers, which can reduce generation of cracks at the plating layers and migration of silver during product formation, and which can greatly reduce the manufacturing cost.
It is another object of the present invention to provide a method for manufacturing a lead frame for a semiconductor package.
To achieve the first object of the present invention, there is provided a lead frame for a semiconductor package including a base metal layer made of copper (Cu), Cu alloy or iron-nickel (Fe-Ni) alloy, an underlying plating layer formed on at least one surface of the base metal layer and made of Ni or Ni alloy, an intermediate plating layer formed on the underlying plating layer to a thickness of about 0.00025 to about 0.1 gm (about 0.1 to about 4 microinches) and made of palladium (Pd) or Pd alloy, and an outer plating layer formed in the intermediate plating layer to a thickness of about 0.05 to about 0.75 xcexcm (about 2 to about 30 microinches) and made of silver (Ag) or Ag alloy.
According to another aspect of the present invention, there is provided a lead frame for a semiconductor package including a base metal layer made of copper (Cu), Cu alloy or iron-nickel (Fe-Ni) alloy, an underlying plating layer formed on at least one surface of the base metal layer and made of Ni or Ni alloy, an intermediate plating layer formed on the underlying plating layer to a thickness of about 0.00025 to about 0.1 xcexcm (about 0.1 to about 4 microinches) and made of palladium (Pd) or Pd alloy, and an outer plating layer formed in the intermediate plating layer to a thickness of about 0.05 to about 0.75 xcexcm (about 2 to about 30 microinches) and made of silver (Ag) or Ag alloy, wherein the intermediate plating layer is formed by applying a modulated current to a plating bath.
To achieve the second object of the present invention, there is provided a method for manufacturing a lead frame for a semiconductor package including the steps of a) providing a base metal layer, b) pre treating the base metal layer, c) forming an underlying plating layer made of Ni or Ni alloy on the base metal layer, d) forming an intermediate plating layer by submerging the resultant structure of the step c) into a plating bath containing Pd or Pd alloy and applying a modulated current having a frequency band of about 1000 to about 20000 Hz and a duty cycle of about 5 to about 45% and a mean current density of about 0.1 to about 3 A/dM2 (amperes per square decimeter) to a plating bath, and e) forming an outer plating layer made of Ag or Ag alloy on the intermediate plating layer.